Welcome to the Laboratory of Computer Architecture and Network Systems (CANS) at the University of Massachusetts Lowell!
The research at CANS lab, led by Prof. Yan Luo, focuses on computer architecture innovations for high performance computing and network systems. The research topics range from chip multiprocessor (CMP) architecture, to network content processing engines, and to network virtualization.
Ongoing Research Projects
OpenFlow Switching is a newly proposed standard allowing for testing new network architecture and protocols in a production network. We leverage the programmability and high performance of Network Processors (NPs) to accelerate the data path of PC-based OpenFlow reference design.
We design and implement a prototype of programmable edge node with hybrid multi-core processors for aggregating computing/storage sites within
GENI. We are one of the 29 teams contributing to
GENI Spiral 1.
Programmability in network equipments enables the adaptability of network protocols and optimization of network performance. We are building a programmable network infrastructure, consisting of programmable routers, software defined radio devices and spectrum analyzers, for the research and education of advanced network technologies.
- Performance Evaluation and Acceleration of an Open Source VPN System on Tolapai Platform, PI: Yan Luo, Intel, 2008-2009
We address the issue of performance inadequacy of Virtual Private Network (VPN) applications. The computational complexity of VPN applications brings challenges for high performance secure networking. We plan to improve the VPN performance with Tolapai platform, taking advantage of Tolapai’s unique converged IA/IXA architecture and on-chip accelerators.
* Design and Performance Evaluation of High Speed Deep Packet Inspection Systems, PI: Yan Luo, 2007-2008
->This research aims to exploit inherent parallelism in regular expression matching algorithms, develop compression schemes to minimize state machine storage, implement reg-ex matching on programmable architectures and evaluate their performance. The long-term goal of this research project is to design high-performance regular expression matching systems that can greatly improve the performance of DPI and other content processing applications.
Past Projects
- Design and Performance Evaluation of High Speed Deep Packet Inspection Systems, PI: Yan Luo, 2007-2009
- Architectural Support for High Performance Pattern Matching, PI: Yan Luo, Intel Corporation, 2006-2007
- Distributed Packet Inspection with Network Processors, PI: Yan Luo, Intel Corporation, 2005-2006
- NePSim: An Open Source Network Processor Simulator, 2004-2007
- Design of Network Applications with Network Processors, 2004-2006
black%: We design and evaluate programmable architectures to speed up complex packet processing workloads. Network processors and FPGAs are the main platforms under study. We also investigate the performance impacts and design trade-offs of integrating programmable accelerators with chip multiprocessors. %
black%: We are designing image sensor devices that transfer image through wireless sensor networks (WSNs). To address the limitation of network bandwidth and power consumption of WSN, we tightly couple low power FPGA with wireless sensor nodes to perform local image processing such as generation of address events. %
Sponsors
We acknowledge the generous supports from
Both governmental agencies and industrial partners are welcome to contact the director of the lab, Prof. Yan Luo, for information, collaboration or sponsored research.